2026.08.26

Congratulations! Mr. Seungbin Kim’s Paper is accepted to T-CAS I 2026

Congratulations! Mr. Seungbin Kim's paper is accepted to IEEE Transactions on Circuits and Systems I (T-CAS I)!We propose a real-time and energy-efficient heterogeneous LOAM processor for efficient LiDAR odometry and mapping under massive keypoint-matching and heterogeneous NLO workloads.The processor employs 3D spherical-bin partitioning and neighboring-bin search, hash-page-based memory management with neighboring-bin caching, and a reconfigurable NLO core for efficient LOAM acceleration.The processor achieves up to 135 FPS and 0.81 mJ/frame, with 99.6% fewer kNN comparisons, 10.5× higher kNN energy efficiency, and 92.3% lower NLO latency.

2026.08.26

Congratulations! Dr. Jueun Jung’s Paper is accepted to JSSC 2026

Congratulations! Dr. Jueun Jung's paper is accepted to IEEE Journal of Solid-State Circuits (JSSC)!We propose ABNP, a real-time multi-modal end-to-end driving processor for efficient CNN-Transformer-Temporal acceleration under dynamic sparsity and temporal-memory overhead.ABNP employs a Sparsity Reasoning Unit, flexible sparse-dense core orchestration with Segmented Aggregation Network,and a Long-/Short-term Memory Unit for memory-efficient temporal attention.ABNP achieves 10.32 frame/s and 71.3 mJ/frame, with 2.67× higher throughput and 218× lower energy than a state-of-the-art driving SoC.

2026.08.26

Congratulations! Dr. Hoichang Jeong’s Paper is accepted to T-CAS I 2026

Congratulations! Dr. Hoichang Jeong's paper is accepted to IEEE Transactions on Circuits and Systems I (T-CAS I)!We propose QUARC, a compact and energy-efficient quad-mode reconfigurable analog-digital hybrid eDRAM CIM processor for efficient ternary-LLM acceleration under costly post-MAC operations and dynamic causal-attention workloads.QUARC employs sign-embedded ternary encoding, an in-column signed-magnitude SAR ADC with comparison skipping, in-column Psum accumulation, and causal-mask-adaptive pipelining for efficient ternary projection and multi-bit attention.QUARC achieves 390 TOPS/W and 48.2 TOPS/W peak macro energy efficiencies for ternary projection and multi-bit attention, respectively, and 101.4 TOPS/W system energy efficiency, with a 1.91 Mb/mm2 macro cell density.

2026.03.24

Congratulations! Mr. Seungbin Kim & Hoichang Jeong’s Paper is accepted in SOVC

Congratulations! Mr. Seungbin Kim* (Ph.D. student) and Hoichang Jeong* (Postdoctoral Researcher) of ISL. received acceptance from SOVC 2026. The paper titled “HCNP: A 70.2 TOPS/W Hybrid CIM-NPU Processor with In-Streaming Processing for Energy-Efficient CNN/Transformer Acceleration in HMD” will be presented June 14-18, 2026 at Hawaii, United States.

2026.03.16

Congratulations! Hoichang Jeong and Seungbin Kim’s paper is accepted to IEEE Journal of Solid-State Circuits!

Congratulations! Hoichang Jeong and Seungbin Kim's paper is accepted to IEEE Journal of Solid-State Circuits. (equal contribution) In this paper, we propose a sparsity-aware analog–digital hybrid eDRAM computing-in-memory (CIM) processor for energy-efficient deep neural network (DNN) acceleration, addressing key efficiency limitations of prior CIM architectures. The design integrates input activation grouping convolution, a hybrid-CIM macro with SAR-Flash ADC and reversed-MAC logic, and sparsity-aware proactive scheduling to improve CIM macro utilization. Fabricated in 28 nm CMOS, the processor achieves 4.59× higher effective computation ratio and improves energy efficiency by 1.55× on ResNet-18 and 10.37× on VGGNet-16 compared with prior CIM processors.

2026.03.02

Congratulations! Jueun received the IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award!

Mr. Jueun Jung (Ph.D. student) of ISL, has received the IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award. The award recognizes a small number of exceptional Ph.D. students worldwide based on academic excellence, research promise, quality of publications, and alignment with the mission of the IEEE SSCS.

2026.02.23

Dongwook’s paper is highlighted by IEEE Transactions on Circuits and Systems I (TCAS-I)!

Congratulations! Dongwook's paper “A Multibit ReRAM Computing-in-Memory Processor With Adaptive Decision Level Nonlinear ADC for Ultra-Low-Energy Keyword Spotting in Mobile Devices” is highlighted by IEEE Transactions on Circuits and Systems I (TCAS-I)! You can watch Dongwook's Presentation Video here.

2026.02.23

Sunhong’s paper is highlighted by IEEE Transactions on VLSI Systems (TVLSI)!

Congratulations! Sunhong's paper "CINELL: An Energy-Efficient Compute-In/Near-Memory eDRAM Processor for Sparse Transformer-Based Large Language Models" is highlighted by IEEE Transactions on VLSI Systems (TVLSI)! This paper introduces CINELL, a compute-in/near-memory eDRAM processor designed to tackle the heavy computation and memory bandwidth demands of transformer-based LLMs. With attention block fusion, a CINM architecture, and compute-in-memory acceleration, CINELL delivers major gains in latency, memory access, and energy efficiency — enabling practical, high-performance LLM inference.

2025.12.01

Congratulations! Jueun and Sangho’s paper is accepted to IEEE International Solid-State Circuits Conference (ISSCC)!

Jueun and Sangho's paper “A 71.3mJ/frame End-to-End Driving Processor with Flexible Heterogeneous Core Orchestration via Sparsity Reasoning” is accepted to IEEE International Solid-State Circuits Conference (ISSCC)! Congratulations!

2025.10.22

Hoichang Jeong’s paper is published to JSSC!

Hoichang Jeong’s Paper “HYTEC: Compact and Energy-Efficient Analog-Digital Hybrid CIM With Transpose Ternary eDRAM” is accepted to JSSC 2025