ISL Background

Intelligent Systems Lab

In the realm of modern computing, our aim is to advance systems based on specialized hardware. Research spans various fields of hardware design, including computer architecture, VLSI, FPGA, hardware/software co-design, and processing-in-memory. We adopt a holistic approach to enhance overall system performance. Our current mission centers on building a high-performance and scalable computing platform for future AI applications.

Research Area

Automotive System

Automotive System

Spatial AI is crucial for autonomous vehicle safety but high computational power consumption reduces driving range. Our research focuses on energy-efficient methods using HW-SW co-design and sensor-friendly AI SoCs to enhance autonomous driving efficiency and safety.

DNN Accelerator

DNN Accelerator

Hand gesture recognition (HGR) using 3D-CNNs and super resolution (SR) with deep neural networks both demand significant computational power, posing challenges for real-time processing on mobile devices. Dedicated ASIC processors are needed to enable efficient HGR and SR on battery-limited devices.

Processing-in-Memory

Processing-in-Memory

Convolutional Neural Networks (CNNs) excel in image and video processing but are limited by high computational and memory demands. Computing-in-Memory (CIM) architecture offers a solution by processing data within on-chip memory, significantly enhancing throughput and energy efficiency for ultra-low-power IoT devices.

Neuromorphic

Neuromorphic

The human brain consumes only 20 mW with 1 billion neurons in computation. Spiking Neural Networks (SNNs) mimic the behavior of biological neural networks to reduce power consumption of Artificial Neural Networks (ANNs). Neuromorphic processors accelerates SNNs for ultra low power hardware such as always-on-sensors, surveilance monitoring, bio-sensor back-end.

Recent Conference Paper

53

Major

ESSERC

Circuit

Processing-in-memory

A 77.1 TOPS/W Simultaneous Refresh-Compute eDRAM CIM Macro with Input-Aware ADC and Effective-Bit Reconfigurable Accumulator

IEEE European Solid-State Electronics Research Conference, Sept. 2026

Hoichang Jeong, Seungbin Kim, Gyumin Choi, Minsoo Kim, and Kyuho Jason Lee

Hoichang JeongSeungbin KimGyumin ChoiMinsoo KimKyuho Jason Lee

52

Major

ESSERC

Circuit

Speech Translation

SSTP: A 13.32 TFLOPS/W End-to-End Simultaneous Speech Translation Processor on Edge Devices

IEEE European Solid-State Electronics Research Conference, Sept. 2026

Bokyoung Seo, Ghangmin Yun, Chaeyoon Kim, Jueun Jung, and Kyuho Jason Lee

Bokyoung SeoGhangmin YunChaeyoon KimJueun JungKyuho Jason Lee

Recent Journal Paper

30

Top-Tier

AFM

Device

Oxygen-Tunnel Indium Tin Oxide Vertical ChannelTransistors with Enhanced Current Density and Reliabilityfor Monolithic 3D Compute-In-Memory Systems

Advanced Functional Materials (AFM), (Early Access), 2026

Hyeonho Gu, Haksoon Jung, Yongwoo Lee, Hoichang Jeong, Yanfeng Zhao, Heesoo Yang, Minho Park, Hyeonjin Lee, Seunghun Baek, Minju Song, Junghwan Kim, Youngmin Jo, Hyunjin Park, Munhyeon Kim, Jae-Joon Kim, Kyuho Jason Lee, Byungjo Kim, and Jimin Kwon

Hoichang JeongKyuho Jason Lee

29

Top-Tier

JSSC

Circuit

Processing-in-memory

SERAH-CIM: Sparsity-Aware Effective Row Activation Analog-Digital Hybrid eDRAM CIM with In-Macro Multi-Row-Multi-Task Control

IEEE Journal of Solid-State Circuits (JSSC), (Early Access), 2026

Hoichang Jeong*, Seungbin Kim*, Dongwook Kim, Jueun Jung, and Kyuho Jason Lee (*equal contribution)

Hoichang JeongSeungbin KimDongwook KimJueun JungKyuho Jason Lee