Circuit
Processing-in-memory
A 30.7 TOPS/W Sparsity-Aware Analog-Digital Hybrid eDRAM CIM by Effective Row Activation with Simultaneous Multi-Row-Multi-Task Control
IEEE European Solid-State Electronics Research Conference(ESSERC), 2025
Hoichang Jeong*, Seungbin Kim*, Jueun Jung, and Kyuho Jason Lee (*equal contribution)