ISL Background

Intelligent Systems Lab

In the realm of modern computing, our aim is to advance systems based on specialized hardware. Research spans various fields of hardware design, including computer architecture, VLSI, FPGA, hardware/software co-design, and processing-in-memory. We adopt a holistic approach to enhance overall system performance. Our current mission centers on building a high-performance and scalable computing platform for future AI applications.

Research Area

Automotive System

Automotive System

Spatial AI is crucial for autonomous vehicle safety but high computational power consumption reduces driving range. Our research focuses on energy-efficient methods using HW-SW co-design and sensor-friendly AI SoCs to enhance autonomous driving efficiency and safety.

DNN Accelerator

DNN Accelerator

Hand gesture recognition (HGR) using 3D-CNNs and super resolution (SR) with deep neural networks both demand significant computational power, posing challenges for real-time processing on mobile devices. Dedicated ASIC processors are needed to enable efficient HGR and SR on battery-limited devices.

Processing-in-Memory

Processing-in-Memory

Convolutional Neural Networks (CNNs) excel in image and video processing but are limited by high computational and memory demands. Computing-in-Memory (CIM) architecture offers a solution by processing data within on-chip memory, significantly enhancing throughput and energy efficiency for ultra-low-power IoT devices.

Neuromorphic

Neuromorphic

The human brain consumes only 20 mW with 1 billion neurons in computation. Spiking Neural Networks (SNNs) mimic the behavior of biological neural networks to reduce power consumption of Artificial Neural Networks (ANNs). Neuromorphic processors accelerates SNNs for ultra low power hardware such as always-on-sensors, surveilance monitoring, bio-sensor back-end.

Recent Conference Paper

47

Major

ESSERC

Circuit

Processing-in-memory

A 30.7 TOPS/W Sparsity-Aware Analog-Digital Hybrid eDRAM CIM by Effective Row Activation with Simultaneous Multi-Row-Multi-Task Control

IEEE European Solid-State Electronics Research Conference (ESSERC), 2025

Hoichang Jeong*, Seungbin Kim*, Jueun Jung, and Kyuho Jason Lee (*equal contribution)

Hoichang JeongSeungbin KimJueun JungKyuho Jason Lee

46

Top-Tier

DAC

Circuit

Multi Camera System

BEVSA: A Real-Time Bird’s-Eye-View Semantic Segmentation Accelerator for Multi-Camera System

ACM/IEEE Design Automation Conference (DAC), 2025

Sangho Lee, Jueun Jung, Wuyoung Jang, Jihyeon Hwang, and Kyuho Lee

Sangho LeeJueun JungWuyoung JangJihyeon HwangKyuho Lee

Recent Journal Paper

28

Top-Tier

JSSC

Circuit

Processing-in-memory

HYTEC: Compact and Energy-Efficient Analog-Digital Hybrid CIM With Transpose Ternary eDRAM

IEEE Journal of Solid-State Circuits (JSSC), (Accepted), 2025

Hoichang Jeong, Seungbin Kim, Jeongmin Shin, and Kyuho Jason Lee

Hoichang JeongSeungbin KimJeongmin ShinKyuho Jason Lee

27

Major

T-VLSI

Circuit

Processing-in-memory

Large-language-Model

CINELL: An Energy-Efficient Compute-in/near-Memory eDRAM Processor for Sparse Transformer-Based Large Language Models

IEEE Transactions on Very Large Scale Integration (T-VLSI), (Accepted), 2025

Sunhong An, Hoichang Jeong, Seungbin Kim, and Kyuho Jason Lee

Sunhong AnHoichang JeongSeungbin KimKyuho Jason Lee