ISL Background

Intelligent Systems Lab

In the realm of modern computing, our aim is to advance systems based on specialized hardware. Research spans various fields of hardware design, including computer architecture, VLSI, FPGA, hardware/software co-design, and processing-in-memory. We adopt a holistic approach to enhance overall system performance. Our current mission centers on building a high-performance and scalable computing platform for future AI applications.

Research Area

Automotive System

Automotive System

Spatial AI is crucial for autonomous vehicle safety but high computational power consumption reduces driving range. Our research focuses on energy-efficient methods using HW-SW co-design and sensor-friendly AI SoCs to enhance autonomous driving efficiency and safety.

DNN Accelerator

DNN Accelerator

Hand gesture recognition (HGR) using 3D-CNNs and super resolution (SR) with deep neural networks both demand significant computational power, posing challenges for real-time processing on mobile devices. Dedicated ASIC processors are needed to enable efficient HGR and SR on battery-limited devices.

Processing-in-Memory

Processing-in-Memory

Convolutional Neural Networks (CNNs) excel in image and video processing but are limited by high computational and memory demands. Computing-in-Memory (CIM) architecture offers a solution by processing data within on-chip memory, significantly enhancing throughput and energy efficiency for ultra-low-power IoT devices.

Neuromorphic

Neuromorphic

The human brain consumes only 20 mW with 1 billion neurons in computation. Spiking Neural Networks (SNNs) mimic the behavior of biological neural networks to reduce power consumption of Artificial Neural Networks (ANNs). Neuromorphic processors accelerates SNNs for ultra low power hardware such as always-on-sensors, surveilance monitoring, bio-sensor back-end.

Recent Conference Paper

50

Top-Tier

SOVC

Circuit

Processing-in-memory

Neural Processor

HCNP: A 70.2 TOPS/W Hybrid CIM-NPU Processor with In-Streaming Processing for Energy-Efficient CNN/Transformer Acceleration in HMD

IEEE/JSAP Symposium on VLSI Technology and Circuits, Jun. 2026

Seungbin Kim*, Hoichang Jeong*, Dongwook Kim, Jiwon Kim, and Kyuho Jason Lee (*equal contribution)

Seungbin KimHoichang JeongDongwook KimJiwon KimKyuho Jason Lee

49

Major

ISCAS

Circuit

Image Processing

A Hardware-Software Co-design of Lightweight Polyp Segmentation Network and Ultra-low-power Processor for Capsule Endoscopy

IEEE International Symposium on Circuits and Systems, May 2026

Ghangmin Yun, Jaekyung Lee, Jiwon Kim, Kyungkeon Chung, Jueun Jung, Bokyoung Seo, Hyejin Lee, Junyoung Park, and Kyuho Jason Lee

Ghangmin YunJiwon KimJueun JungBokyoung SeoKyuho Jason Lee

Recent Journal Paper

29

Top-Tier

JSSC

Circuit

Processing-in-memory

SERAH-CIM: Sparsity-Aware Effective Row Activation Analog-Digital Hybrid eDRAM CIM with In-Macro Multi-Row-Multi-Task Control

IEEE Journal of Solid-State Circuits (JSSC), (Early Access), 2026

Hoichang Jeong*, Seungbin Kim*, Dongwook Kim, Jueun Jung, and Kyuho Jason Lee (*equal contribution)

Hoichang JeongSeungbin KimDongwook KimJueun JungKyuho Jason Lee

28

Top-Tier

JSSC

Circuit

Processing-in-memory

HYTEC: Compact and Energy-Efficient Analog-Digital Hybrid CIM With Transpose Ternary eDRAM

IEEE Journal of Solid-State Circuits (JSSC), (Early Access), 2026

Hoichang Jeong, Seungbin Kim, Jeongmin Shin, and Kyuho Jason Lee

Hoichang JeongSeungbin KimJeongmin ShinKyuho Jason Lee