Circuit
Processing-in-memory
TeSLIC: A 28-nm Ternary Sparsity-aware Latch-based Computing-in-Memory Macro
IEEE Journal of Solid-State Circuits (JSSC), (Early Access), 2026
Myoung Kim*, Hoichang Jeong*, Woo-Seok Kim, Yesong Jeong, Junyoung Park, Yong Kyu Lee, Min Woo Ryu, Kyuho Jason Lee, and Kyung Rok Kim (*equal contribution)



















