Congratulations! Dr. Hoichang Jeong’s paper is accepted to IEEE Transactions on Circuits and Systems I (T-CAS I)!

We propose QUARC, a compact and energy-efficient quad-mode reconfigurable analog-digital hybrid eDRAM CIM processor for efficient ternary-LLM acceleration under costly post-MAC operations and dynamic causal-attention workloads.

QUARC employs sign-embedded ternary encoding, an in-column signed-magnitude SAR ADC with comparison skipping, in-column Psum accumulation, and causal-mask-adaptive pipelining for efficient ternary projection and multi-bit attention.

QUARC achieves 390 TOPS/W and 48.2 TOPS/W peak macro energy efficiencies for ternary projection and multi-bit attention, respectively, and 101.4 TOPS/W system energy efficiency, with a 1.91 Mb/mm² macro cell density.