Congratulations! Hoichang Jeong and Seungbin Kim’s paper is accepted to IEEE Journal of Solid-State Circuits. (equal contribution)

In this paper, we propose a sparsity-aware analog–digital hybrid eDRAM computing-in-memory (CIM) processor for energy-efficient deep neural network (DNN) acceleration, addressing key efficiency limitations of prior CIM architectures.

The design integrates input activation grouping convolution, a hybrid-CIM macro with SAR-Flash ADC and reversed-MAC logic, and sparsity-aware proactive scheduling to improve CIM macro utilization.

Fabricated in 28 nm CMOS, the processor achieves 4.59× higher effective computation ratio and improves energy efficiency by 1.55× on ResNet-18 and 10.37× on VGGNet-16 compared with prior CIM processors.