ISL Background

Intelligent Systems Lab

In the realm of modern computing, our aim is to advance systems based on specialized hardware. Research spans various fields of hardware design, including computer architecture, VLSI, FPGA, hardware/software co-design, and processing-in-memory. We adopt a holistic approach to enhance overall system performance. Our current mission centers on building a high-performance and scalable computing platform for future AI applications.

Research Area

Automotive System

Automotive System

Spatial AI is crucial for autonomous vehicle safety but high computational power consumption reduces driving range. Our research focuses on energy-efficient methods using HW-SW co-design and sensor-friendly AI SoCs to enhance autonomous driving efficiency and safety.

DNN Accelerator

DNN Accelerator

Hand gesture recognition (HGR) using 3D-CNNs and super resolution (SR) with deep neural networks both demand significant computational power, posing challenges for real-time processing on mobile devices. Dedicated ASIC processors are needed to enable efficient HGR and SR on battery-limited devices.

Processing-in-Memory

Processing-in-Memory

Convolutional Neural Networks (CNNs) excel in image and video processing but are limited by high computational and memory demands. Computing-in-Memory (CIM) architecture offers a solution by processing data within on-chip memory, significantly enhancing throughput and energy efficiency for ultra-low-power IoT devices.

Neuromorphic

Neuromorphic

The human brain consumes only 20 mW with 1 billion neurons in computation. Spiking Neural Networks (SNNs) mimic the behavior of biological neural networks to reduce power consumption of Artificial Neural Networks (ANNs). Neuromorphic processors accelerates SNNs for ultra low power hardware such as always-on-sensors, surveilance monitoring, bio-sensor back-end.

Recent Conference Paper

55

Major

ISICAS

Circuit

Vision Transformer

Depth Estimation

An Energy-Efficient Monocular Depth Estimation Processor with Local Group Token Merging and On-the-Fly Sparse Speculation

IEEE International Symposium on Integrated Circuits and Systems, Dec. 2026

Junghyun Yoo, Seungbin Kim, Ghangmin Yun, Bokyoung Seo, Jueun Jung, and Kyuho Jason Lee

Junghyun YooSeungbin KimGhangmin YunBokyoung SeoJueun JungKyuho Jason Lee

54

Major

ISICAS

Circuit

PointCloud Neural Network

EMPSA: A 2.98mJ/frame PointMamba Accelerator for Real-time 3D Point-Cloud Segmentation

IEEE International Symposium on Integrated Circuits and Systems, Dec. 2026

Chaeyoon Kim, Bokyoung Seo, Ghangmin Yun, Seungbin Kim, Jueun Jung, and Kyuho Jason Lee

Chaeyoon KimBokyoung SeoGhangmin YunSeungbin KimJueun JungKyuho Jason Lee

Recent Journal Paper

36

Major

T-CAS II

Circuit

Vision Transformer

Depth Estimation

An Energy-Efficient Monocular Depth Estimation Processor with Local Group Token Merging and On-the-Fly Sparse Speculation

IEEE Transactions on Circuits and Systems II (T-CAS II): Express Briefs, 2026

Junghyun Yoo, Seungbin Kim, Ghangmin Yun, Bokyoung Seo, Jueun Jung, and Kyuho Jason Lee

Junghyun YooSeungbin KimGhangmin YunBokyoung SeoJueun JungKyuho Jason Lee

35

Major

T-CAS II

Circuit

PointCloud Neural Network

EMPSA: A 2.98mJ/frame PointMamba Accelerator for Real-time 3D Point-Cloud Segmentation

IEEE Transactions on Circuits and Systems II (T-CAS II): Express Briefs, 2026

Chaeyoon Kim, Bokyoung Seo, Ghangmin Yun, Seungbin Kim, Jueun Jung, and Kyuho Jason Lee

Chaeyoon KimBokyoung SeoGhangmin YunSeungbin KimJueun JungKyuho Jason Lee